Many types of integrated circuit products, such as microcontrollers, are customized by the provision of a customized operating instruction set contained in an on-chip read-only memory (ROM) array. The customized instruction set may be developed by the chip maker or the customer and then permanently "programmed" in to the ROM during the chip fabrication process. The ROM may be an array of addressable cells with an operable transistor fabricated at those cells in the array designated to read as a logic "one" when addressed and with no transistor or an inoperable transistor fabricated at those cells designated to read as a logic "zero" when addressed. For example, in the case of a cell designated as a logic "one", a field effect transistor may be fabricated such that when the cell is addressed by applying voltages to the source, drain and gate, current will flow through the channel which can be sensed as a logic "one". Conversely, for the case of a cell designated as a logic "zero", an inoperable field effect transistor may be fabricated such that when the source, drain and gate voltages are applied during addressing, no current will flow thereby indicating a logic "zero". The inoperable field effect transistor may be created by fabricating a gate oxide layer which is sufficiently thick that a channel cannot be created between the source and the drain when a normal reading voltage is applied to the gate. The inoperable transistor may also be created by fabricating cells in which one of the source or drain diffusions is missing or in which the source and drain diffusions are so widely spaced as to prevent channel sufficiently wide formation therebetween.
While a ROM array is very useful for a customized final product, because it is permanently "programmed" during manufacture, it is not well suited for development products. Simply put, when a change in the instruction set is required during development, an entirely different ROM array may be required on-chip. A new ROM array in turn will require the refabrication of at least part of the chip to "reprogram" the memory ,cells. This problem is solved by the use of an erasable read-only memory (EPROM) array which can be programmed and erased during chip development. EPROM cells store a bit of information as a quantity of electrons on a floating gate structure insulatively formed between the channel area and the control gate of the field effect transistor. A charged floating gate raises the threshold voltage of the field effect transistor channel above the voltage normally applied to the control gate during the read operation, thereby storing a logic "zero." An uncharged floating gate does not alter the threshold voltage of the channel of the field effect transistor, and therefore a normal gate reading voltage will exceed the threshold voltage thereby storing a logic "one." As known in the art, these EPROM cells are commonly programmed by charging the floating gate through hot electron injection and erased by exposure to ultraviolet light. Due to the increased complexity of the EPROM cell (which not only requires the additional floating gate and the associated interlevel insulators but also an erasing window and its associated structures), the EPROM has serious disadvantages when used as part of the final version of the customized product. This is especially true when it is recognized that once the final product design is ready, the need for an erasable array is essentially eliminated.
Thus, in many cases a development chip using an EPROM device must be designed and fabricated and once the final implementation is arrived at, a final production version must be designed and fabricated using a ROM array. This process, aside from any changes to the logic and power circuitry on the chip, almost requires the design and fabrication two versions of the same overall product. In most cases, an inefficient duplication of design and fabrication efforts results.
Thus, a need has arisen for devices and methods for reducing the amount of duplicative efforts required to provide the customer with both development and production versions of a customized integrated circuit.